====== File Organisation ======
===== Overview =====
  * Primary and secondary design units can be split into several files
  * Advantages of
    * Several Packages
      * Modularisation and reuse aspects (IEEE, corporate, project packages)
      * Separation of synthesizable from simulation only VHDL
    * Package / Package body Separation
      * No recompilation of the design hierarchy
 if body (implementation) changed
    * Entity / Architecture Separation
      * System design (top level, structural) independent from implementation
      * Several modelling alternatives (e.g. behavioral, RTL) possible
    * Several top level configurations
      * Adjust design to goal of simulation
      * Comparison of alternative architectures

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=== Notes ===
VHDL offers several possibilities of implementing hierarchy. 

The language introduces the main hierarchy into the design with the philosophy of entity/architecture pairs and their instantiation as components. This leads to a strict separation of interface and implementation. 

With the help of packages, libraries and concise naming conventions it is possible to manage huge designs with a plenty of files. Switching between the different implementations during simulation is done with the configuration mechanism.
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