library ieee; use ieee.std_logic_1164.all; use work.P_DISPLAY.all; entity TB_EXP_CTRL is end TB_EXP_CTRL; architecture TEST of TB_EXP_CTRL is constant PERIOD : time := 1 sec/8192; --constant PERIOD : time := 5 ns; component EXP_CTRL port(CLK : in std_ulogic; RESET : in std_ulogic; TIMER_GO : in std_ulogic; EXP_TIME : in T_DIGITS; EXPOSE : buffer std_ulogic; NO_PICS : buffer T_DIGITS); end component; signal W_CLK : std_ulogic := '0'; signal W_RESET : std_ulogic; signal W_TIMER_GO : std_ulogic; signal W_EXP_TIME : T_DIGITS; signal W_EXPOSE : std_ulogic; signal W_NO_PICS : T_DIGITS; begin DUT : EXP_CTRL port map( CLK => W_CLK, RESET => W_RESET, TIMER_GO => W_TIMER_GO, EXP_TIME => W_EXP_TIME, EXPOSE => W_EXPOSE, NO_PICS => W_NO_PICS); W_CLK <= not W_CLK after PERIOD/2; STIMULI : process begin W_RESET <= '1'; W_TIMER_GO <= '1'; W_EXP_TIME <= (0,6,4); -- EXPOSE: '0', NO_PICS: (0,0,0) wait for 3*PERIOD; W_RESET <= '0'; W_TIMER_GO <= '0'; -- no changes wait for 3*PERIOD; W_TIMER_GO <= '1'; wait for 1*PERIOD; W_TIMER_GO <= '0'; wait for 1*PERIOD; W_TIMER_GO <= '1'; wait for 1*PERIOD; W_TIMER_GO <= '0'; wait for 1*PERIOD; W_TIMER_GO <= '1'; wait for 1*PERIOD; W_TIMER_GO <= '0'; wait for 1 sec/64; -- EXPOSE: '1', NO_PICS: (0,0,1) wait for 10 * PERIOD; W_EXP_TIME <= (5,1,2); for I in 1 to 100 loop W_TIMER_GO <= '1'; wait for 1*PERIOD; W_TIMER_GO <= '0'; wait for 1 sec/512; end loop; -- NO_PICS: (1,0,1) wait; end process STIMULI; end TEST; configuration CFG_TB_EXP_CTRL of TB_EXP_CTRL is for TEST end for; end CFG_TB_EXP_CTRL;