library ieee; use ieee.std_logic_1164.all; use work.P_DISPLAY.all; entity EXP_CTRL is -- system signals: CLK, RESET -- control signals: TIMER_GO, EXPOSE -- data signals: EXP_TIME, NO_PICS end EXP_CTRL; architecture RTL of EXP_CTRL is -- The EXP_TIME signal must be mapped to a limit for the -- exposure timer, i.e. an internal signal is needed procedure INC_DIGIT ( DIGIT : inout integer; CARRY : inout std_ulogic) is begin if CARRY = '1' then if DIGIT /= 9 then DIGIT := DIGIT + 1; CARRY := '0'; else DIGIT := 0; end if; -- OVERFLOW end if; -- CARRY = '1' end INC_DIGIT; begin -- architecture MAPPER: process (EXP_TIME) begin -- default assignment for all outputs to avoid latches if EXP_TIME = (5,1,2) then LIMIT <= 0; elsif EXP_TIME = (2,5,6) then LIMIT <= 1; -- Map all other exposure times to the corresponding limit end if; end process MAPPER; EXP_TIMER: process (CLK, RESET) variable COUNT_16 : integer range ; -- Counter to generate 1/512s timesteps variable TIMER : integer range ; -- Counter for the final exposure time begin if RESET = '1' then -- Reset all registers elsif (CLK'event and CLK = '1') then if EXPOSE = '1' then -- Exposure timer -- 2 cascaded counters: 1st -> 1/512s timesteps -- 2nd -> exposure time elsif TIMER_GO = '1' then -- Start exposure timer end if; end if; end process EXP_TIMER; PIC_COUNT: process(CLK, RESET) variable LAST_EXPOSE : std_ulogic; variable CARRY : std_ulogic; variable DIGIT : integer; begin if RESET = '1' then LAST_EXPOSE := '0'; NO_PICS <= (0, 0, 0); elsif CLK'event and CLK = '1' then -- Check for rising edge of EXPOSE signal CARRY := '1'; for I in T_DIGITS'low to T_DIGITS'high loop -- Increment the picture counter end loop; end if; -- Rising EXPOSE edge end if; -- Rising clock edge end process PIC_COUNT; end RTL;