library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;

entity TB_DISP_DRV is
end TB_DISP_DRV;

architecture TEST of TB_DISP_DRV is
  component DISP_DRV
    port(ERROR     : in std_ulogic;
         SHOW_TIME : in std_ulogic;
         NO_PICS   : in T_DIGITS;
         EXP_TIME  : in T_DIGITS;
         DISPLAY   : out T_DISPLAY);
    end component;

  signal W_ERROR : std_ulogic :='0';
  signal W_SHOW_TIME : std_ulogic :='0';
  signal W_NO_PICS : T_DIGITS;
  signal W_EXP_TIME : T_DIGITS;
  signal W_DISPLAY : T_DISPLAY;
  
begin
  DUT : DISP_DRV
    port map(
      ERROR     => W_ERROR,
      NO_PICS   => W_NO_PICS,
      EXP_TIME  => W_EXP_TIME,
      SHOW_TIME => W_SHOW_TIME,
      DISPLAY   => W_DISPLAY);
  
  STIMULI : process
  begin
    -- DISPLAY = (0,0,0)
    wait for 30 ns;
    
    W_NO_PICS <= (0,0,0);
    W_EXP_TIME <= (5,0,0);
    -- no changes
    wait for 20 ns;
    
    for I in 1 to 10 loop
      W_NO_PICS <= (0,0,I);
      -- DISPLAY = (0,0,1)..(0,0,E)
      wait for 20 ns;
    end loop;
    
    W_SHOW_TIME <= '1';
    -- DISPLAY = (5,0,0)
    wait for 20 ns;
    
    W_EXP_TIME <= (0,6,0);
    W_NO_PICS <= (4,0,0);
    -- DISPLAY = (0,6,0)
    wait for 20 ns;
    
    W_SHOW_TIME <= '0';
    -- DISPLAY = (4,0,0)
    wait for 20 ns;
    
    W_ERROR <= '1';
    -- DISPLAY = (E,E,E)
    wait for 20 ns;
    
    W_SHOW_TIME <= '1';
    -- no changes
    wait for 20 ns;
    
    W_ERROR <= '0';
    -- DISPLAY = (0,6,0)
    wait for 20 ns;
    
    W_SHOW_TIME <= '0';
    -- DISPLAY = (4,0,0)
    wait for 20 ns;
    
    wait;
  end process STIMULI;
  DISPLAY_DIGIT(W_DISPLAY);
end TEST;

configuration CFG_TB_DISP_DRV of TB_DISP_DRV is
  for TEST
  end for;
end CFG_TB_DISP_DRV;