library ieee;
use ieee.std_logic_1164.all;

entity MAIN_CTRL is
  -- system signals: CLK, RESET
  -- control signals: TRIGGER, EXPOSE, MOTOR_READY, MOTOR_ERROR
  -- output signals: ERROR, TIMER_GO, MOTOR_GO
end MAIN_CTRL;

architecture RTL of MAIN_CTRL is
  -- The state machine has to control the exposure process:
  -- While in IDLE state, the device waits for a trigger signal
  -- Then the exposure controller is started and the main controller
  -- has to wait for the end of the exposure. Please note, that the
  -- exposure controller needs 1 clock cycle to react on input signal
  -- changes!
  -- After the picture has been taken, the film transport must be
  -- initiated and the camera has to wait for the motor to finish
  -- If an error occurs, the controller shall enter a BROKEN state
  -- to prevent any further damage to the film
  
  -- Signals to store the state information:
  signal STATE      : T_STATE;
  signal NEXT_STATE : T_STATE;

begin
  -- process to calculate the next state
  begin
    -- Keep the old state as default action
    -- Check all transitions
    case STATE is
      when IDLE =>
      when TAKE_PIC =>
      when DELAY =>
      when WAIT_EXP_TIME =>
      -- Other states
      when others =>
        NULL;
    end case;
  end process;
  
  -- Clocked process to update the FSM registers
  begin
    if (RESET = '1') then
      -- Default system state
    elsif (CLK'event and CLK = '1') then
      -- Update of register values
    end if; -- end of clocked process
  end process;
  
  -- Concurrent statements to drive the output signals with STATE select
  ERROR <= '1' when BROKEN,
           '0' when others;
end RTL;