-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    encoders_decoders.vhd                                    #
-- #                                                                          #
-- # Component  :    decNen : N-Bit Decoder. The input word selects           #
-- #                          which output bit is asserted if allowed         #
-- #                          by enable. This module can be used as           #
-- #                          demultiplexer.                                  #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.all;

-- decNen Entity Description
entity decNen is
   generic(N: INTEGER := 2);
   port(
      DIN: in unsigned(log2(N)-1 downto 0);
      EN: in std_ulogic;
      DOUT: out unsigned(N-1 downto 0)
   );
end decNen;

-- decNen Architecture Description
architecture rtl of decNen is
  signal DIN_integer: integer range 0 to N-1;
begin
  DIN_integer <= Conv_Integer('0' & DIN,0);
  
  DECODER_process: process (DIN_integer, EN)
  BEGIN
    FOR i IN 0 TO N-1 LOOP
      IF EN = '1' AND (DIN_integer = i) THEN
        DOUT(i) <= '1';
      ELSE
        DOUT(i) <= '0';
      END IF;
    END LOOP;
  end process DECODER_process;
end rtl;