-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_comparators.vhd                                     #
-- #                                                                          #
-- # Component  :    test_comparators : Test Bench for various comparatos.    #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test_comparators IS
END test_comparators;

ARCHITECTURE rtl OF test_comparators IS

COMPONENT eqN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      B: in unsigned(N-1 downto 0);
      EQ: out std_ulogic
   );
end COMPONENT;

COMPONENT gleNs is
   generic(N: INTEGER := 4);
   port(
      A: in signed(N-1 downto 0);
      B: in signed(N-1 downto 0);
      EQ,GT,LT: buffer std_ulogic
   );
end COMPONENT;

COMPONENT gleNu is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      B: in unsigned(N-1 downto 0);
      EQ,GT,LT: out std_ulogic
   );   
END COMPONENT;

 FOR ALL : eqN USE ENTITY WORK.eqN(rtl);
 FOR ALL : gleNs USE ENTITY WORK.gleNs(rtl);
 FOR ALL : gleNu USE ENTITY WORK.gleNu(rtl);
 
 CONSTANT N : integer := 8;
 SIGNAL A_u,B_u : unsigned(N-1 downto 0);
 SIGNAL A_s,B_s : signed(N-1 downto 0);
 SIGNAL EQ0,EQ1,GT1,LT1,EQ2,GT2,LT2 : std_ulogic;
 
 BEGIN

Equality : eqN 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A_u,
		       B=>B_u,
		       EQ=>EQ0
		      );	 

Comparator_unsigned : gleNu 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A_u,
		       B=>B_u,
		       EQ=>EQ1,
		       GT=>GT1,
		       LT=>LT1
		      );	 

Comparator_signed : gleNs 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       A=>A_s,
		       B=>B_s,
		       EQ=>EQ2,
		       GT=>GT2,
		       LT=>LT2
		      );	 
		      

A_u <= "10101000",
       "01011001" AFTER 100 ns, 
       "11011011" AFTER 200 ns, 
       "01101001" AFTER 300 ns;
B_u <= "00111000",
       "01001011" AFTER 100 ns, 
       "01010001" AFTER 200 ns, 
       "11001001" AFTER 300 ns;
A_s <= "10101000",
       "01011001" AFTER 100 ns, 
       "11011011" AFTER 200 ns, 
       "01101001" AFTER 300 ns;
B_s <= "00111000",
       "01001011" AFTER 100 ns, 
       "01010001" AFTER 200 ns, 
       "11001001" AFTER 300 ns;

END rtl;