Generate a VHDL TESTBENCH from a VHDL ENTITY

Just copy your ENTITY in the textbox below and decide if you want to get a Synopsys VSS-Startfile and a VSS-Tracefile.

 The ENTITY must be written in correct VHDL syntax!

VHDL Code from the entity: 
Generate Synopsys VSS-Startfile and VSS-Tracefile? 
  yes(y) or no(n)?: 

If problems occur, please contact me vhdl@lrs.eei.uni-erlangen.de