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VHDL Testbench Generator

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Copyright:    Universität Erlangen-Nürnberg
   Lehrstuhl für Rechnergestützten Schaltungsentwurf
   Prof. Dr.-Ing. Wolfram H. Glauert
   Paul-Gordan-Str. 5, 91052 Erlangen
   Tel.: 09131-8523102
   Fax: 09131-8523111
   Email: vhdl@lrs.e-technik.uni-erlangen.de
   W3: http://www.vhdl-online.de
   To use our Testbench Generator just click here.

   After writing an VHDL model the designer must
   write a VHDL testbench to simulate the module.

   The designer should use his time for thinking
   about the design verification and not for writing
   the VHDL testbench template.

   So we decided to write a C-program which 
   generates such a template file. 

   The program needs a correct VHDL entity, reads 
   the entity information (ports, generics, ...) and then
   generates the testbench using our Style Guide. .

   Everyone knows that it is horrible to parse VHDL
   so we don't support the following features:
   - Type-, Subtype- and Subprogramdefinitions in
       the entity section
   - Keyword 'signal' in PORT and GENERIC declarations
   - ??? (you can tell us, if you found one)

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