VHDL Modellbibliothek

Parameters for the Divider

A short interface specification:

The input width of the model are parameterizable.
The inputs and outputs will have the same bit width.
The algorithm is implemented asynchronous without flipflops.

Interface:

dvd : Input port for the dividend
dvs : Input port for the divisor
quot : Output port for the quotient
rest : Output port for the remainder (2's complement)

Filename without extension '.vhd' an

   Filename (without .vhd):

Integer value for the bit width:

   integer value       :

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