VHDL Model-Lib

Parameters for the Carry-Lookahead-Adder/Subtractor with arithmetic overflow

A short interface specification:

The model adds or subtracts depending on the input add_sub. The model is not cascadable. The inputs have to be in complement of 2.

add_sub = 1 -> s = a + b
add_sub = 0 -> s = a - b

Ports:


a, b          : binary values in the 2-complement representation
add_sub       : mode:
                add_sub = '1' : addition
                add_sub = '0' : subtraction
overflow      : arithmetic overflow
                overflow = '1': 
                overflow = '0': no overflow
s             : computed sum/difference

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