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...	Synthesizeable VHDL-Model-Library		...
	Copyright:	Universität Erlangen-Nürnberg    Lehrstuhl für Rechnergestützten Schaltungsentwurf    Prof. Dr.-Ing. Wolfram H. Glauert    Paul Gordan Str. 5, 91052 Erlangen    Tel.: 09131-8523102    Fax: 09131-8523111    Email: vhdl@lrs.e-technik.uni-erlangen.de    W3: http://www.vhdl-online.de/
	More models you will find at: CorePool
		We have implemented parameterizeable VHDL models and Testbenches.    You type in the portwidth and receive the synthesizeable VHDL description    (and the accordingly testbench and a trace file    for the SYNOPSYS VHDL-simulator).    Here you find our package with specifc types.    Content: Carry-Lookahead-Adder Carry-Lookahead-Adder/Subtractor Array-Divider Array-Divider/Multiplier FIFO1(First In First Out): data output synchron to the clock edge FIFO2: data output asynchron to the clock edge Arbiter(1): bus- and grant-request realized as one signal Parity-Generator Synchron, loadable counter Synchron counter with hard upper limit Synchron, seperable counter, with loadable upper limit    Models, testbenches and Synopsys VSS Trace-files are displayed    in the browser as single ASCII-file.    Please store it in THREE seperated files...
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